Conventional computer systems include a processor (not shown) coupled to a variety of memory devices, including read-only memories (“ROMs”) which traditionally store instructions for the processor, and a system memory to which the processor may write data and from which the processor may read data. The processor may also communicate with an external cache memory, which is generally a static random access memory (“SRAM”). The processor also communicates with input devices, output devices, and data storage devices.
Processors generally operate at a relatively high speed. Processors such as the Pentium® and Pentium II® microprocessors are currently available that operate at clock speeds of at least 400 MHz. However, the remaining components of existing computer systems, with the exception of SRAM cache memory, are not capable of operating at the speed of the processor. For this reason, the system memory devices, as well as the input devices, output devices, and data storage devices, are not coupled directly to the processor bus. Instead, the system memory devices are generally coupled to the processor bus through a memory controller, bus bridge or similar device, and the input devices, output devices, and data storage devices are coupled to the processor bus through a bus bridge. The memory controller allows the system memory devices to operate at a clock frequency that is substantially lower than the clock frequency of the processor. Similarly, the bus bridge allows the input devices, output devices, and data storage devices to operate at a frequency that is substantially lower than the clock frequency of the processor. Currently, for example, a processor having a 300 MHz clock frequency may be mounted on a mother board having a 66 MHz clock frequency for controlling the system memory devices and other components.
Access to system memory is a frequent operation for the processor. The time required for the processor, operating, for example, at 300 MHz, to read data from or write data to a system memory device operating at, for example, 66 MHz, greatly slows the rate at which the processor is able to accomplish its operations. Thus, much effort has been devoted to increasing the operating speed of system memory devices.
System memory devices are generally dynamic random access memories (“DRAMs”). Initially, DRAMs were asynchronous and thus did not operate at even the clock speed of the motherboard. In fact, access to asynchronous DRAMs often required that wait states be generated to halt the processor until the DRAM had completed a memory transfer. However, the operating speed of asynchronous DRAMs was successfully increased through such innovations as burst and page mode DRAMs, which did not require that an address be provided to the DRAM for each memory access. More recently, synchronous dynamic random access memories (“SDRAMs”) have been developed to allow the pipelined transfer of data at the clock speed of the motherboard. However, even SDRAMs are typically incapable of operating at the clock speed of currently available processors. Thus, SDRAMs cannot be connected directly to the processor bus, but instead must interface with the processor bus through a memory controller, bus bridge, or similar device. The disparity between the operating speed of the processor and the operating speed of SDRAMs continues to limit the speed at which processors may complete operations requiring access to system memory.
A solution to this operating speed disparity has been proposed in the form of a packetized memory device known as a SLDRAM memory device. In the SLDRAM architecture, the system memory may be coupled to the processor, either directly through the processor bus or through a memory controller. Rather than requiring that separate address and control signals be provided to the system memory, SLDRAM memory devices receive command packets that include both control and address information. The SLDRAM memory device then outputs or receives data on a data bus that may be coupled directly to the data bus portion of the processor bus.
An example of a computer system 10 using the SLDRAM architecture is shown in FIG. 1. The computer system 10 includes a processor 12 having a processor bus 14 coupled to three SLDRAM packetized dynamic random access memory devices 16a-c through a memory controller 18. The computer system 10 also includes one or more input devices 20, such as a keypad or a mouse, coupled to the processor 12 through the processor bus 14, a bus bridge 22, and an expansion bus 24, such as an Industry Standard Architecture (“ISA”) bus or a Peripheral Component Interconnect (“PCI”) bus. The input devices 20 allow an operator or an electronic device to input data to the computer system 10. One or more output devices 30 are coupled to the processor 12 to display or otherwise output data generated by the processor 12. The output devices 30 are coupled to the processor 12 through the expansion bus 24, bus bridge 22 and processor bus 14. Examples of output devices 24 include printers and a video display units. One or more data storage devices 38 are coupled to the processor 12 through the processor bus 14, bus bridge 22, and expansion bus 24 to store data in or retrieve data from storage media (not shown). Examples of storage devices 38 and storage media include fixed disk drives floppy disk drives, tape cassettes and compact-disk read-only memory drives.
In operation, the processor 12 sends a data transfer command via the processor bus 14 to the memory controller 18, which, in turn, communicates with the memory devices 16a-c via the system memory bus 23 by sending the memory devices 16a-c command packets that contain both control and address information. Data is coupled between the memory controller 18 and the memory devices 16a-c through a data bus portion of the system memory bus 23. During a read operation, data is transferred from the SLDRAMs 16a-c over the memory bus 23 to the memory controller 18 which, in turn, transfers the data over the processor 14 to the processor 12. The processor 12 transfers write data over the processor bus 14 to the memory controller 18 which, in turn, transfers the write data over the system memory bus 23 to the SLDRAMs 16a-c. Although all the memory devices 16a-c are coupled to the same conductors of the system memory bus 23, only one memory device 16a-c at a time reads or writes data, thus avoiding bus contention on the memory bus 23. Bus contention is avoided by each of the memory devices 16a-c on the system memory 22 having a unique identifier, and the command packet contains an identifying code that selects only one of these components.
The computer system 10 also includes a number of other components and signal lines that have been omitted from FIG. 1 in the interests of brevity. For example, as explained below, the memory devices 16a-c also receive a command clock signal to provide internal timing signals, a data clock signal clocking data into the memory device 16, and a FLAG signal signifying the start of a command packet.
A typical command packet CA<0:39> for a SLDRAM packetized DRAM is shown in FIG. 2 and is formed by four packet words CA<0:9>, each of which contains 10 command bits. As will be explained in more detail below, each packet word CA<0:9> is applied on a command-address bus CA that includes ten lines CA0-CA9. In FIG. 2, the four packet words CA<0:9> comprising a command packet CA<0:39> are designated PW1-PW4. The first packet word PW1 contains 7 bits identifying the packetized DRAM 16a-c that is the intended recipient of the command packet. Each of the packetized DRAMs is provided with a unique ID code that is compared to the 7 ID bits in the first packet word PW1. Thus, although all of the packetized DRAMs 16a-c will receive the command packet, only the packetized DRAM 16a-c having an ID code that matches the 7 ID bits of the first packet word PW1 will respond to the command packet.
The remaining 3 bits of the first packet word PW1 as well as 3 bits of the second packet word PW2 comprise a 6 bit command. Typical commands are read and write in a variety of modes, such as accesses to pages or banks of memory cells. The remaining 7 bits of the second packet word PW2 and portions of the third and fourth packet words PW3 and PW4 comprise a 20 bit address specifying a bank, row and column address for a memory transfer or the start of a multiple bit memory transfer. In one embodiment, the 20-bit address is divided into 3 bits of bank address, 10 bits of row address, and 7 bits of column address.
Although the command packet shown in FIG. 2 is composed of 4 packet words each containing up to 10 bits, it will be understood that a command packet may contain a lesser or greater number of packet words, and each packet word may contain a lesser or greater number of bits.
One of the memory devices 16a is shown in block diagram form in FIG. 3. Each of the memory devices 16a-c includes a clock generator circuit 40 that receives a command clock signal CMDCLK and generates an internal clock signal ICLK and a large number of other clock and timing signals to control the timing of various operations in the memory device 16. The memory device 16a also includes a command buffer 46 and an address capture circuit 48, which receive the internal clock signal ICLK, a command packet CA<0:9> on a 10-bit command-address bus 50, and a FLAG signal on line 52. A memory controller (not shown) or other device normally transmits the command packet CA<0:9> to the memory device 16a in synchronism with the command clock signal CMDCLK. As explained above, the command packet CA<0:39>, which generally includes four 10-bit packet words, contains control and address information for each memory transfer. The FLAG signal identifies the start of a command packet, and it also signals the start of an initialization sequence. The command buffer 46 receives the command packet from the command-address bus 50, and compares at least a portion of the command packet to identifying data from an ID register 56 to determine if the command packet is directed to the memory device 16a or some other memory device 16b, 16c. If the command buffer 46 determines that the command packet is directed to the memory device 16a, it then provides the command words to a command decoder and sequencer 60. The command decoder and sequencer 60 generates a large number of internal control signals to control the operation of the memory device 16a during a memory transfer.
The address capture circuit 48 also receives the command packet from the command-address bus 50 and outputs a 20-bit address corresponding to the address information in the command packet. The address is provided to an address sequencer 64, which generates a corresponding 3-bit bank address on bus 66, a 10-bit row address on bus 68, and a 7-bit column address on bus 70. The column address and row address are processed by column and row address paths 73, 75 as will be described in more detail below.
One of the problems of conventional DRAMs is their relatively low speed resulting from the time required to precharge and equilibrate circuitry in the DRAM array. The packetized DRAM 16a shown in FIG. 3 largely avoids this problem by using a plurality of memory banks 80, in this case eight memory banks 80a-h. After a read from one bank 80a, the bank 80a can be precharged while the remaining banks 80b-h are being accessed. Each of the memory banks 80a-h receives a row address from a respective row latch/decoder/driver 82a-h. All of the row latch/decoder/drivers 82a-h receive the same row address from a predecoder 84 which, in turn, receives a row address from either a row address register 86 or a refresh counter 88 as determined by a multiplexer 90. However, only one of the row latch/decoder/drivers 82a-h is active at any one time, as determined by bank control logic 94 as a function of a bank address from a bank address register 96.
The column address on bus 70 is applied to a column latch/decoder 100, which supplies I/O gating signals to an I/O gating circuit 102. The I/O gating circuit 102 interfaces with columns of the memory banks 80a-h through sense amplifiers 104. Data is coupled to or from the memory banks 80a-h through the sense amplifiers 104 and the I/O gating circuit 102 and a data path subsystem 108, which includes a read data path 110 and a write data path 112. The read data path 110 includes a read latch 120 that stores data from the I/O gating circuit 102.
In the memory device 16a shown in FIG. 3, 64 bits of data are stored in the read latch 120. The read latch then provides four 16-bit data words to an output multiplexer 122 that sequentially supplies each of the 16-bit data words to a read FIFO buffer 124. Successive 16-bit data words are clocked into the read FIFO buffer 124 by a clock signal DCLK generated by the clock generator 40. The 16-bit words are then clocked out of the read FIFO buffer 124 by a clock signal RCLK obtained by coupling the DCLK signal through a programmable delay circuit 126. The read FIFO buffer 124 sequentially applies the 16-bit words to a driver circuit 128 in synchronism with the RCLK signal. The driver circuit, in turn, applies the 16-bit data words to a data bus 130. The driver circuit 128 also applies the data clock signal DCLK to a clock line 132. The programmable delay circuit 126 is programmed during initialization of the memory device so that the DCLK signal has the optimum phase relative to DCLK signal for the DCLK signal to clock the read data into the memory controller (not shown), processor, or other device.
The write data path 112 includes a receiver buffer 140 coupled to the data bus 130. The receiver buffer 140 sequentially applies 16-bit words from the data bus 130 to four input registers 142, each of which is selectively enabled by a signal from a clock generator circuit 144. The clock generator circuit generates these enable signals responsive to the data clock DCLK, which, for write operations, is applied to the memory device 16a on line 132 from the memory controller, processor, or other device. As with the command clock signal CMDCLK and command packet CA<0:9>, the memory controller or other device (not shown) normally transmits the data to the memory device 16a in synchronism with the data clock signal DCLK. The clock generator 144 is programmed during initialization to adjust the timing of the clock signal applied to the input registers 142 relative to the DCLK signal so that the input registers can capture the write data at the proper times. Thus, the input registers 142 sequentially store four 16-bit data words and combine them into one 64-bit data word applied to a write FIFO buffer 148. The data are clocked into the write FIFO buffer 148 by a clock signal from the clock generator 144, and the data are clocked out of the write FIFO buffer 148 by an internal write clock WCLK signal. The WCLK signal is generated by the clock generator 40. The 64-bit write data are applied to a write latch and driver 150. The write latch and driver 150 applies the 64-bit write data to one of the memory banks 80a-h through the I/O gating circuit 102 and the sense amplifiers 104.
As mentioned above, the memory device includes registers that store device parameters particular to the operation of that specific memory chip configuration. For example, the registers may store data indicative of the device configuration, data transfer format, speed capability, serial number, manufacturer, clock speed, etc. By way of further example, a register storing data indicative of the clock speed may be read to provide clock speed signals, MBPS400-800, that are used to time various signals as described in U.S. application Ser. No. 08/994,461, “Method and System for Processing Pipelined Memory Commands,” to Manning, which is incorporated herein by reference.
These registers may be programmed with appropriate data, using relatively simple circuitry so that relatively little circuitry must be added to the memory device to write data to the registers. Also, registers can be programmed during manufacture or test, so that no additional circuitry may be required to program the registers. However, circuitry must be added to the memory device to read the data from the registers. The need to add this readout circuitry can be problematic because the large amount of circuitry already present in state of the art memory devices minimizes the space available on a semiconductor die to add this additional circuitry. The readout circuitry can easily be added by making the size of the die larger. Doing so, however, reduces the number of dies that can be manufactured from each wafer, thus increasing the cost of such memory devices. A need therefore exists to be able to read data from on-board registers in memory devices without using a great deal of read-out circuitry.
Although the foregoing discussion is directed to reading register data in packetized memory devices, such as SLDRAMs, similar problems exist in other types of memory devices.